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Data Sheet No. PD60225 revA
IRMCK203
High Performance Sensorless Motion Control IC
Features
! ! ! ! ! ! ! ! ! ! ! ! ! !
Complete Sensorless control IC for Permanent Magnet AC motors No phase voltage feedback sensing required Sinusoidal current waveform with Synchronously Rotating Frame closed loop current control High starting torque and smooth speed ramping Direct interface to IR2175 current sensing high voltage IC Auto Retry at startup with configurable starting torque Versatile loss minimization Space Vector PWM Serial communication interface (RS232C, RS422, SPI) 2 I C serial interface to 1k bit serial EEPROM for parameter storage for stand alone operation Phase loss/Overcurrent/Overvoltage protection 7-bit discrete I/O for sequencing and status monitor Integrated brake IGBT control for dc bus voltage limitation ServoDesigner
TM
Product Summary
Max Clock input Sensorless control computation time Speed operating range (typical) Speed control resolution Adjustable current limit at start-up Programmable retry on start-up 33.3 MHz 10 sec max 5% to 100% 15 bit full range 15 bit full range max 16 trials
Over current, speed, phase loss, dc bus fault protection PWM carrier frequency IR2175 Current feedback data resolution Inverter leg current sensing (optional) RS232C speed Optional RS422 communication Max SPI Clock Package: QFP80 16 bit/33MHz 10bit 12bit up to 57.6 Kbps up to 1 Mbps 8 MHz
tool for easy operation
Parallel interface for microcontroller expansion
Description
IRMCK203 is a high performance digital motion control IC for Sensorless AC permanent magnet motor application. Control is based on closed loop vector control for sinusoidal Back EMF motors. With IRMCK203, the users can readily build a high performance Sensorless drive system without any programming effort and minimum start-up time. Built-in unique start-up and ramping algorithm enables wide application. This IC is versatile enough that the users can configure and optimize system performance according to the needs of each application. With International Rectifier iMOTION products including high voltage ICs such as IR2175 current sensing IC and IRAM series of Intelligent IGBT module in combination with IRMCK203, the end result is a fully optimized system with reduced electronics component counts. This simplifies the design for low cost Sensorless drive modules. IRMCK203 can be easily adapted to various permanent magnet motors through ServoDesignerTM tool, which is the fully configurable graphic user interface tool.
This document is the property of International Rectifier and may not be copied or distributed without expressed consent.
IRMCK203 Overview
IRMCK203 is a new International Rectifier integrated circuit device designed for one-chip solution for complete closed loop current and velocity control of a high performance Sensorless drive for PM motors. Unlike a traditional microcontroller or DSP, IRMCK203 does not require any programming to complete complex Sensorless algorithm development. Combined with International Rectifier's high voltage gate drive and current sensing IC, the user can implement complete speed control of PM motors with minimum component count and virtually no design effort. In addition to Sensorless closed loop speed control operation, features such as Start-up retry, Phase Loss detection, Low Loss PWM, Regeneration Braking control and various drive protections are all implemented inside IRMCK203. Analog and digital I/Os can also be configured. Host communication logic contains Asynchronous Communication Interface for RS232C or RS422 communication interface, a fast slave SPI interface and an 8 bit wide Host Parallel Interface. All communication ports have the same access capability to the host register set. The users can write to, and read from the predefined registers to configure and monitor the drive through these communication ports.
IRMCK203 Main functions
* * * * * * * * * * * * * * * * * Complete closed loop current control based on Synchronously Rotating Frame Field Orientation (using Rotor Angle Observer) Closed loop velocity control based on estimated speed Configurable parameters (PI controller gains, PI output limit range, current feedback scaling, PWM carrier frequency) provide adaptation to various PM motors Built-in Sensorless control logic for start-up, ramping, and running conditions Auto Retry (programmable) on start-up with configurable torque current limit Analog reference input (can be used for speed reference) RS232C/RS422 reference input Full dynamic braking control for DC bus voltage limitation Cycle-by-cycle on/off Control for Brake IGBT Loss minimization Space Vector PWM with deadtime insertion Build-in two IR2175 current sensing IC interfaces Phase Loss, Overcurrent (GATEKILL input), Overvoltage, Undervoltage, Overspeed protection Low cost serial 12bit A/D interface with multiplexer and sample/hold circuit Optional Inverter Leg (low side) current sensing in lieu of IR2175 IC 4 channel analog output (PWM) Local EEPROM for startup initialization of internal data/parameters through host register interface AT24C01A, 128X8 Versatile host communication interface RS232C or RS422 host interface Fast SPI slave host interface with multi-drop capability Parallel Host interface (total 12 pins) Multiplexed data/address bus Address Enable RD/WR Discrete I/Os for Standalone mode operation STARTSTOP (Input) ESTOP (Input)
*
*
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IRMCK203
DIR (Input) FLTCLR (Input) FAULT (Output) SYNC (Output) REDLED (Output) GREENLED (Output)
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IRMCK203
Table of Contents
Overview........................................................................................................................................................................... 2 IRMCK203 Main functions .............................................................................................................................................. 2 IRMCK203 Block Diagrams............................................................................................................................................. 7 Basic Block Diagram .................................................................................................................................................... 7 Input/Output of IRMCK203.......................................................................................................................................... 8 Application Connections............................................................................................................................................. 12 IC Crystal Clock Circuitry .......................................................................................................................................... 13 PLL Clock Circuitry.................................................................................................................................................... 14 Low Pass Filter............................................................................................................................................................ 14 Implementing the Low Pass Filter Shield ............................................................................................................... 15 Cp Rp and Cs Component Values........................................................................................................................... 15 PLL Reset.................................................................................................................................................................... 15 DC Electrical Characteristics and Operating Conditions ................................................................................................ 16 Absolute Maximum Ratings........................................................................................................................................ 16 Recommended Operating Conditions ......................................................................................................................... 16 DC Characteristics ...................................................................................................................................................... 17 Common Quiescent and Leakage Current .................................................................................................................. 17 Input Characteristics - Non Schmitt Inputs ................................................................................................................ 17 Input Characteristics - Schmitt Inputs ........................................................................................................................ 17 Output Characteristics................................................................................................................................................. 17 Output Characteristics OSC2CLK .............................................................................................................................. 18 Pin and I/O Characteristic Table ................................................................................................................................. 19 Power Consumption .................................................................................................................................................... 21 AC Electrical Characteristics and Operating Conditions ................................................................................................ 22 System Level AC Characteristics................................................................................................................................ 22 Sync Pulse to Sync Pulse Timing............................................................................................................................ 22 FAULT and REDLED Response to GATEKILL ................................................................................................... 23 Host Interface AC Characteristics............................................................................................................................... 24 SPI Timing .............................................................................................................................................................. 24 Host Parallel Timing ................................................................................................................................................... 25 Host Parallel Read Cycle......................................................................................................................................... 25 Host Parallel Write Cycle........................................................................................................................................ 26 Discrete I/O Electrical Characteristics ........................................................................................................................ 27 Motion Peripheral Electrical Characteristics............................................................................................................... 28 PWM Electrical Characteristics .............................................................................................................................. 28 IR2175 Interface ..................................................................................................................................................... 28 Analog Interface Electrical Characteristics................................................................................................................. 29 ADC Timing............................................................................................................................................................ 29 PLL Interface Electrical Characteristics...................................................................................................................... 30 Appendix A Host Register Map .................................................................................................................................. 31 Register Access ........................................................................................................................................................... 31 Host Parallel Access................................................................................................................................................ 31 SPI Register Access ................................................................................................................................................ 31 RS-232 Register Access.......................................................................................................................................... 31 Write Register Definitions .......................................................................................................................................... 36 PwmConfig Register Group (Write Registers) ....................................................................................................... 36 CurrentFeedbackConfig Register Group (Write Registers) .................................................................................... 37 SystemControl Register Group (Write Registers)................................................................................................... 38 TorqueLoopConfig Register Group (Write Registers)............................................................................................ 38 VelocityControl Register Group (Write Registers)................................................................................................. 39
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FaultControl Register Group (Write Registers) ...................................................................................................... 40 SystemConfig Register Group (Write Registers).................................................................................................... 41 EepromControl Registers (Write Registers)............................................................................................................ 42 ClosedLoopAngleEstimator Registers (Write Registers)........................................................................................ 43 OpenLoopAngleEstimator Registers (Write Registers) .......................................................................................... 44 StartupAngleEstimator Registers (Write Registers)................................................................................................ 44 StartupRetrial Registers (Write Registers) .............................................................................................................. 45 PhaseLossDetect Registers (Write Registers) ......................................................................................................... 47 D/AConverter Registers (Write Registers) ............................................................................................................. 47 Factory Test Register (Write Register) ................................................................................................................... 48 Read Register Definitions ........................................................................................................................................... 49 SystemStatus Register Group (Read Registers) ...................................................................................................... 49 DcBusVoltage Register Group (Read Registers) .................................................................................................... 49 FocDiagnosticData Register Group (Read Registers)............................................................................................. 50 FaultStatus Register Group (Read Registers).......................................................................................................... 51 VelocityStatus Register Group (Read Registers) .................................................................................................... 52 CurrentFeedbackOffset Register Group (Read Registers) ...................................................................................... 53 EepromStatus Registers (Read Registers)............................................................................................................... 53 FOCDiagnosticDataSupplement Register Group (Read Registers) ........................................................................ 54 ProductIdentification Registers (Read Registers) ................................................................................................... 55 Factory Register (Read Register) ............................................................................................................................ 55 Appendix B Package ................................................................................................................................................... 56
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IRMCK203
Table of Figures
Figure 1: IRMCS2031 Simplified Blocks......................................................................................................................... 7 Figure 2: Input/Output of IRMCK203 .............................................................................................................................. 8 Figure 3: Application Connection of IRMCK203........................................................................................................... 12 Figure 4: Oscillator Circuit ............................................................................................................................................. 13 Figure 5: PLL Low Pass Filter Shielding........................................................................................................................ 14 Figure 6: System Level SYNC To SYNC Timing .......................................................................................................... 22 Figure 7: FAULT and REDLED Response to GATEKILL............................................................................................ 23 Figure 8: SPI Timing....................................................................................................................................................... 24 Figure 9: Host Parallel Read Cycle ................................................................................................................................. 25 Figure 10: Host Parallel Write Cycle .............................................................................................................................. 26 Figure 11: Discrete I/O Timing....................................................................................................................................... 27 Figure 12: PWM Timing................................................................................................................................................. 28 Figure 13: IR2175 Interface............................................................................................................................................ 28 Figure 14: Top Level ADC Timing ................................................................................................................................ 29
Table of Tables
Table 1: Typical Values for the Clock Circuit ................................................................................................................ 13 Table 2: PLL Test Pin Assignments................................................................................................................................ 14 Table 3: PLL Low Pass Filter Values ............................................................................................................................. 15 Table 4: Absolute Maximum Ratings ............................................................................................................................. 16 Table 5: Recommended Operating Conditions ............................................................................................................... 16 Table 6: DC Characteristics ............................................................................................................................................ 17 Table 7: Non Schmitt Input Characteristics .................................................................................................................... 17 Table 8: Schmitt Input Characteristics ............................................................................................................................ 17 Table 9: Output Characteristics....................................................................................................................................... 17 Table 10: Output Characteristics OSC2CLK .................................................................................................................. 18 Table 11: Pin and I/O Characteristics ............................................................................................................................. 21 Table 12: IRMCK203 Power Consumption.................................................................................................................... 21 Table 13: System Level SYNC to SYNC Timing........................................................................................................... 22 Table 14: FAULT and REDLED Response to GATEKILL ........................................................................................... 23 Table 15: SPI Timing ...................................................................................................................................................... 24 Table 16: Host Parallel Read Cycle Timing.................................................................................................................... 25 Table 17: Host Parallel Write Cycle Timing................................................................................................................... 26
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IRMCK203
IRMCK203 Block Diagrams
Basic Block Diagram
Figure 1 shows the basic block diagram of the IRMCK203 surrounded by International Rectifiers' ICs. Host communications are provided over SPI, RS-232C or Host parallel ports. Two current sensing ICs (IR2175) and a three phase high voltage gate drive typically implement the high voltage / current interface between the IRMCK203 IC and motor. The IRMCK203 can operate in a "stand-alone" mode without the host controller. utilized to load motor-specific parameters into the IC. A serial EEPROM would be
AC Power
Analog Monitor
EEPROM
IRMCS2031 IRMCK203
select
Analog Speed Reference
4 channel D/A RS232C or RS422 RAMP Host Register Interface
A/D interface DC bus dynamic brake control
BRAKE
A/D
MUX
DC bus feedback
+ -
+ + -
e
Rotor Angle/ speed Estimator
j
Space Vector PWM
Dead time
IR2136
Host Controller
SPI Interface
FAULT
Plug-N-DriveTM IGBT module IRAMY20UP60A
Parallel Interface
Configuration Registers Monitoring Registers
e
j
2/3
Period/Duty counters Period/Duty counters
IR2175 IR2175
Motor
Figure 1: IRMCS2031 Simplified Blocks Configurable parameters are provided to tailor design to various applications (motor and load). These configurable parameters can be modified via the host register interface through the communication interface. In the IRMCK203 product, a design spread sheet is provided to aid the user for ease of drive start-up, the spread sheet will input high level application data such as motor name plate information, max speed, current limit, speed and current regulator bandwidth, base on this information the program will generate the required configurable parameters. Detail on Drive commissioning is described in the IRMCK203 Application Developer's Guide. All logic and algorithms are pre-programmed, and the user does not need to make any effort to develop code, alleviating the tedious design process. If needed, the user can configure the drive to tailor the control per specific
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IRMCK203
needs to meet the required specification. This configuration can be easily done by accessing the host register interface through the communication interface.
Input/Output of IRMCK203
The I/O signals are shown in Figure 2. The interface signals are divided into sub-groups. assignment, please refer to appendix (Pin definition). For detailed pin
Crystal
OSC1CLK OSC2CLK BYPASSMODE PWMUH PWMUL PWMVH PWMVL PWMWH PWMWL BRAKE FLTCLROUT GATEKILL
PLL Clock Control
PLLTEST XPD CHGO AVDD LPVSS VSSHC
PWM gate signal Interface
SPI Interface RS232C Interface
SPICLK SPIMISO SPIMOSI SPICSN
IFB[0-1]
IR2175 Interface D/A Interface (PWM output)
DAC[0-3] TX RX BAUDSEL
IRMCK203
ADCLK ADOUT ADCONVST ADMUX[0-2] RESSAMPLE
Parallel Interface
HPD[0-7] HPOEN HPWEN HPCSN HPA
A/D Interface
Discrete I/O
STARTSTOP ESTOP FLTCLR SYNC FAULT DIR RESETN
System Reset
Serial EEPROM LED/Status
SCA SCL REDLED GREENLED
Figure 2: Input/Output of IRMCK203
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IRMCK203
Host Interface Group
Signal SPICLK SPIMISO SPIMOSI SPICSN HPOEN HPWEN HPD [7:0] HPA HPCSN TX RX Input (I) / Output (O) I O I I I I I/O I I O I Low (L) / High (H) True Asserted Positive edge sensitive L L L H L Function SPI clock Master input and slave output Master output and slave input SPI chip select Parallel data output enable Parallel data write cycle identification Parallel data Parallel data address cycle identification Chip select RS-232 data out RS-232 data in RS-232 baud rate: 00 = 19.3K bps; 01 = 38.4K bps 10 = 57.6K bps; 11 = 1.031250M bps Start of PWM cycle 33.333 MHz output of PLL. This signal has no phase relationship with the OSC1CLK or OSC2CLK inputs.
BAUDSEL[1:0]
I
H
SYNC CLK1XOUT
O O
L -
Discrete I/O Group
Signal STARTSTOP DIR FAULTCLR ESTOP PWEN SYNC FAULT Input (I) / Output (O) I I I I O O O Low (L) / High (H) True Asserted H H H H H H H Function Start / Stop command edge sensitive Forward/Reverse Direction command, level sensitive Fault Clear Emergency Stop, state sensitive PWM enable/disable state SYNC pulse Fault state
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IRMCK203
Motion Peripheral Group
Signal PWMUH PWMUL PWMVH PWHVL PWMWH PWMWL BRAKE GATEKILL IFB0 IFB1 Input (I) / Output (O) O O O O O O O I I I Low (L) / High (H) True Asserted Function PWM phase U high side PWM phase U low side PWM phase V high side PWM phase V low side PWM phase W high side PWM phase W low side IGBT gate When asserted, negates all six PWM signals, host writeable Channel 0 (phase V) Channel 1 (phase W)
-
L Varies, Based on Write Register 0x0C Bit 7 -
Analog Interface Group
Signal ADCLK ADOUT DAC [3:0] ADCONVST RESSAMPLE ADMUX0 ADMUX1 Input (I) / Output (O) O I O O O O O H H Low (L) / High (H) True Asserted Negative Edge Sensitive L Function Clock to ADS7818 Serial data from ADS7818 Diagnostic DAC Conversion start to ADS7818 Sample/hold control signal channel 0 A/D converter Analog input MUX select Analog input MUX select
PLL Interface Group
Signal XPD RESETN BYPASSCLK BYPASSMODE OSC1CLK OSC2CLK PLLTEST CHGO LPVSS Input (I) / Output (O) I I I I I I I I/O I/O Low (L) / High (H) True Asserted L L H H H Function PLL reset Digital logic reset Internal test pin - force to logic low Internal test pin - force to logic low 33.33 MHz crystal input 33.33 MHz crystal input Internal test pin - force to logic low Low pass filter Low pass filter ground
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IRMCK203
Miscellaneous Group
Signal SCA SCL GREENLED REDLED Input (I) / Output (O) I/O O O O Low (L) / High (H) True Asserted Positive Edge Sensitive H H Function EEPROM data EEPROM clock LED signal LED signal
Power Supply Group
Signal LVDD AVCC MVDD VSSHC Function IC Logic +3.3V power supply IC Analog +3.3V power supply IC Phase +3.3V Lock Loop power supply IC Phase Lock Loop power supply return
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IRMCK203
Application Connections
Typical application connection is shown in Figure 3. In order to complete a Sensorless drive control, all necessary components are shown in connection to IRMCK203. Although this is a typical hardware configuration, users can customize the design without the effort of modifying code.
System Clock
33MHz Crystal
OSC1CLK OSC2CLK SPICLK SPIMISO SPIMOSI SPICSN TX RX PWMUH PWMUL PWMVH PWMVL PWMWH PWMWL BRAKE GATEKILL FAULTCLR BAUDSEL[1:0] HPD[0-7] HPOEN,HPWEN HPCSN,HPA STARTSTOP IFB0 Isolator 5V IFB1 Isolator PO
SPI Interface
Gate Drive & IGBTs
To PC
MAX232A
Optional microcontroller Discrete I/O switches
8051 uP
5V PO
Motor Phase Shunt
IR2175 IR2175
DIR ESTOP FLTCLR SYNC FAULT SCA SCL REDLED GREENLED
IRMCK203 Digital Control IC
Motor Phase Shunt
Motor Current Sensing
Analog Speed Reference
ADCLK ADOUT ADCONVST
LED Serial EEPROM Bi-Color LED
AT24C01A
ADS7818 4051
DC bus voltage 2-leg shunt current sensing (optional)
ADMUX0 ADMUX1 ADMUX2 RESSAMPLE DAC0 DAC1 CHGO BYPASSCLK BYPASSMODE PLLTEST LPVSS
Analog Output
DAC2 DAC3
PLL Low Pass FIlter
Figure 3: Application Connection of IRMCK203
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IRMCK203
IC Crystal Clock Circuitry
The clock input to the IC is a 33.33 MHz crystal oscillator. required to terminate the crystal to the IC. Two shunt capacitors and a possibly a series resistor is
The values of the R/C will vary based on actual PCB attributes, and some empirical analysis may be required to get the PLL to start oscillating. Once oscillating, verify that the signal waveform at the OSC1CLK and OSC2CLK pins are sinusoidal rather than trapezoidal. Refer to Table 1 for suggested R/C values. Most low-cost crystals can be used in this application. An example is a Citizen Part number CM309B33.333MABJT available from Digi-Key under part number 300-4160-1-ND.
OSC1CLK
IRMCK203
C1 XTAL R2
OSC2CLK R1 C2
Figure 4: Oscillator Circuit
Component XTAL C1 C2 R1 R2
Value 33.33 5 5 0 3.9K
Units MHz pF pF
Table 1: Typical Values for the Clock Circuit
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IRMCK203
PLL Clock Circuitry
The IRMCK203 contains a PLL that creates a 2X and 4X clock from the input 33.33 MHz input clock pin. are a number of pins on the IC allocated for factory testing purposes that need to be connected to VSS. Table 2 shows required PCB signal connections for these pins. Pin Number 1 7 PCB Connection VSS VSS There
Table 2: PLL Test Pin Assignments
Low Pass Filter
The low pass filter for this PLL resides between the CHGO and LPVSS pins. required to implement this filter: Cp, Rp and Cs. Figure 5 shows how to place these components around the IC. A shield should be placed below Rp, Cp and Cs made out of copper etch. Three passive components are
S h ie ld e d b y L P V S S CHGO
Rp IR M C K 2 0 3 Cs
Cp
LPVSS
Figure 5: PLL Low Pass Filter Shielding
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IRMCK203
Implementing the Low Pass Filter Shield
Make all connections between CHGO, Rp, Cp, Cs and LPVSS as short as possible. Create the underlining shield by "copper filling" a larger area in the signal plane of the PCB. Connect this shield to the LPVSS pin of the IC. Do not connect this shield to signal ground (VSS).
Cp Rp and Cs Component Values
For a typical FR4 PCB, the values of the passive components are shown in Table 3.
Component Rp Cp Cs
Value 3.9K 1000 Not Installed
Units pF -
Table 3: PLL Low Pass Filter Values
PLL Reset
There are two reset pins on the IC, XPD and RESETN both low true. XPD holds the PLL circuitry in reset when low. Upon XPD going high, the PLL circuitry begins to lock onto the 33.33 MHz clock input. The PLL circuit may take up to 1 msec to become stable. RESETN asserted low holds the internal DSP logic in reset. Upon RESETN going high, the IC digital logic becomes active. RESET should be held low during and at least 1 ms after XPD goes high false to hold the internal logic in reset while the PLL becomes stable.
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IRMCK203 DC Electrical Characteristics and Operating Conditions
Absolute Maximum Ratings
Note: VSS = 0 Volt PARAMETER Power Supply Voltage Input Voltage Input Voltage Output Voltage Output Current per Pin Storage Temperature SYMBOL VDD VI VI VO IOUT Tstg LIMITS VSS-0.3 to 4.0 VSS-0.3 to VDD+0.5 VSS-0.3 to 7 VSS-0.3 to VDD+0.5 +/- 30 -65 to 150 UNIT S V V V V mA C NOTE
Non 5 Volt Tolerant Pins (Table 11) Only on 5 Volt Tolerant Pins (Table 11)
Table 4: Absolute Maximum Ratings
Recommended Operating Conditions
Note: VSS = 0 Volt PARAMETER Power Supply Voltage Input Voltage Input Voltage Ambient Temperature SYMBOL VDD VI VI Ta MIN 3.0 VSS VSS -40 TYP 3.3 MAX 3.6 VDD 5.5 85 UNITS V V V C NOTE
Non 5 Volt Tolerant Pins (Table 11) Only on 5 Volt Tolerant Pins (Table 11) Note 2
Table 5: Recommended Operating Conditions Notes: 2. The ambient temperature range is recommended for Tj= -40 to 125 C
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IRMCK203
DC Characteristics Common Quiescent and Leakage Current
PARAMETER Quiescent Current Input Leakage Current SYMBOL IDDS CONDITIONS VI=VDD or VSS VDD=MAX IOH=IOL=0 Ta=Tj=85C VDD=MAX VIH=VDD VIL=VSS MIN TYP MAX .35 UNITS uA
ILI
-1
-
1
uA
Table 6: DC Characteristics
Input Characteristics - Non Schmitt Inputs
PARAMETER High Level Input Voltage Low Level Input Voltage SYMBOL VIH1 VIL1 CONDITIONS VDD=MAX VDD=MIN MIN 2.0 TYP MAX 0.8 UNITS V V
Table 7: Non Schmitt Input Characteristics
Input Characteristics - Schmitt Inputs
PARAMETER High Level Input Voltage Low Level Input Voltage Hysteresis Voltage SYMBOL VT1+ VT1VH1 CONDITIONS VDD=MAX VDD=MIN VDD=MIN MIN 1.1 0.6 0.1 TYP MAX 2.4 1.8 UNITS V V V
Table 8: Schmitt Input Characteristics
Output Characteristics
PARAMETER High Level Output Voltage Low Level Output Voltage SYMBOL VOH3 VOL3 CONDITIONS VDD=MIN IOH=-12mA VDD=MIN IOH = 12mA MIN VDD - 0.4 TYP MAX VSS + 0.4 UNITS V V
Table 9: Output Characteristics
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IRMCK203
Output Characteristics OSC2CLK
PARAMETER High Level Output Voltage Low Level Output Voltage SYMBOL LVOH LVOL CONDITIONS VDD=MIN IOH=-530uA VDD=MIN IOH = 730uA MIN VDD - 0.4 TYP MAX VSS + 0.4 UNITS V V
Table 10: Output Characteristics OSC2CLK
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IRMCK203
Pin and I/O Characteristic Table
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Pin Name INTERNAL IC RESISTOR TERMINATION 40K-240K Pull Down Pin Type I O I P O P I I P P P P O P I I I O O P O O O P O O P O O I I I I P O P I O I O 5.50 VOLT TOLERANT INPUT YES YES YES YES YES YES INPUT DC CHARACTERISTIC TABLE Table 8 Table 7 Table 7 Table 7 Table 8 Table 8 Table 8 Table 8 Table 8 Table 8 Table 8 Table 8 Table 8 OUTPUT DC CHARACTERISTIC TABLE Table 9 Table 10 Table 9 Table 9 Table 9 Table 9 Table 9 Table 9 Table 9 Table 9 Table 9
BYPASSMODE FLTCLROUT OSC1CLK LVDD OSC2CLK VSS PLLTEST XPD VSSHC MVDD VSSHC AVDD CHGO LPVSS DIR RESETN SPICSN REDLED GREENLED VSS PWMWL PWMWH PWMVL LVDD PWMVH PWMUL VSS PWMUH BRAKE BAUDSEL0 GATEKILL IFB1 IFB2 LVDD CLK1XOUT VSS SPIMOSI SPIMISO SPICLK TX
20K-120K Pull Down
20K - 120K Pull Down 20K -120K Pull Up
20K - 120K Pull Down 20K -120K Pull Up
Table 9
Table 9 Table 9
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IRMCK203
Pin Number 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 Pin Name INTERNAL IC RESISTOR TERMINATION 20K -120K Pull Up Pin Type I I P O P O O O O O I O O I I I P O O P O O O B B B P B B P B B B I I I I 5.50 VOLT TOLERANT INPUT YES YES YES YES YES YES YES YES YES YES INPUT DC CHARACTERISTIC TABLE Table 8 Table 8 Table 8 Table 8 Table 8 Table 8 Table 7 Table 7 Table 7 Table 7 Table 7 Table 7 Table 7 Table 7 Table 8 Table 8 Table 8 Table 8 OUTPUT DC CHARACTERISTIC TABLE Table 9 Table 9 Table 9 Table 9 Table 9 Table 9 Table 9 Table 9 Table 9 Table 9 Table 9 Table 9 Table 9 Table 9 Table 9 Table 9 Table 9 Table 9 Table 9 Table 9 Table 9 -
RX BAUDSEL1 LVDD ADMUX0 VSS ADMUX1 ADMUX2 RESSAMPLE ADCONVST ADCLK ADOUT SYNC FAULT STARTSTOP ESTOP FLTCLR LVDD PWMEN DAC3 VSS DAC2 DAC1 DAC0 HPD0 HPD1 HPD2 VDD HPD3 HPD4 VSS HPD5 HPD6 HPD7 HPOEN HPWEN HPA HPCSN
20K -120K Pull Down 20K -120K Pull Down 20K -120K Pull Down
20K -120K Pull Down 20K -120K Pull Down 20K -120K Pull Down 20K -120K Pull Down 20K -120K Pull Down 20K -120K Pull Down 20K -120K Pull Down 20K -120K Pull Down
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IRMCK203
Pin Number 78 79 80 Pin Name INTERNAL IC RESISTOR TERMINATION Pin Type P O B 5.50 VOLT TOLERANT INPUT INPUT DC CHARACTERISTIC TABLE Table 7 OUTPUT DC CHARACTERISTIC TABLE Table 9 Table 9
VSS SCL SDA
20K -120K Pull Up
Table 11: Pin and I/O Characteristics
Power Consumption
PARAMETER PTotal SYMBOL PTOTAL CONDITIONS VDD=3.3V MIN TYP 1.2 MAX UNITS WATT
Table 12: IRMCK203 Power Consumption
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IRMCK203
AC Electrical Characteristics and Operating Conditions
System Level AC Characteristics
Sync Pulse to Sync Pulse Timing
t5
SYNC
Current Feedback sampling
t1 t2 t3 t4
Angle Estimation
Closed loop current control
Space Vector PWM
Figure 6: System Level SYNC To SYNC Timing
SYMBOL t1 t2 t3 t4 t5
DESCRIPTION Current Feedback Sample Delay Using IR2175 for current feedback Using Leg Shunts for current feedback (optional) Rotor Angle Estimation Time Current and velocity control Space Vector PWM calculation time Total SYNC to SYNC minimum time Table 13: System Level SYNC to SYNC Timing
TIME (sec) 4.3 2.0 4.9 3.1 2.3 14.6 (max)
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IRMCK203
FAULT and REDLED Response to GATEKILL
t5 GATEKILL t1 FAULT t2 REDLED t4 FLTCLR t3
Figure 7: FAULT and REDLED Response to GATEKILL
SYMBOL t1 t2 t3 t4 t5
DESCRIPTION FAULT Response to GATEKILL REDLED Response to GATEKILL FAULT Response to FLTCLR REDLED Response to FLTCLR GATEKILL Pulse Width
MIN
TYP 640 640 190 190
UNITS ns ns ns ns ns
485
Table 14: FAULT and REDLED Response to GATEKILL
This document is the property of International Rectifier and may not be copied or distributed without expressed consent.
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IRMCK203
Host Interface AC Characteristics
SPI Timing
tSCLK SCLK
CS
tCSS tMOSIS
MOSI
MISO tMISO tMISOZ
Figure 8: SPI Timing
SYMBOL fSCLK tSCLK tCSS tMOSIS tMISO tMIOZ
DESCRIPTION SPI Clock Frequency SPI Clock Period CS to SCLK high Setup MOSI to SCLK low Setup SCLK to MISO Valid CS to MISO High Impedance
MIN 125 20 20 73 15
MAX 8
35
UNITS MHz ns ns ns ns ns
Table 15: SPI Timing
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IRMCK203
Host Parallel Timing
Host Parallel Read Cycle
tHPCSN HPCSN
HPWEN
tHPWENS tHPA tHPAS tAHPD
HPA
HPD[7:0] tHPOENS HPOEN
tHPZD tHPOEN
VALID tHPDZ
Figure 9: Host Parallel Read Cycle
SYMBOL tHPCSN tHPWENS tHPAS tAHPD THPZD tHPDZ tHPOENS tHPOEN
DESCRIPTION HPCSN Period HPWENS Setup HPA Setup HPD[7:0] Access HPD[7:0] Active HPD[7:0] High Impedance HPOEN Setup HPOEN Period
MIN 70 40 40 60 0 0 40 70
MAX
105 9 6
UNIT S ns ns ns ns ns ns ns ns
NOTE
Note 3
Note 3
Table 16: Host Parallel Read Cycle Timing Note: 3. HPOEN, HPWEN must be stable before the high to low transition of HPCSN.
This document is the property of International Rectifier and may not be copied or distributed without expressed consent.
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IRMCK203
Host Parallel Write Cycle
tHPCSN
HPCSN tHPWENS HPWEN tHPAS
tHPWEN
tHPA
HPD[7:0] tHPD[7:0]S HPOEN tHPOENS
tHPD[7:0]
tHPOEN
Figure 10: Host Parallel Write Cycle
SYMBOL tHPCSN tHPWENS tHPWEN tHPAS tHPA tHPD[7:0] tHPOENS tHPOEN
DESCRIPTION HPCSN Period HPWENS Setup HPWEN Period HPA Setup HPA Period HPD[7:0] Setup HPOEN Setup HPOEN Period
MIN 70 40 70 -10 70 -10 40 70
MAX
UNITS ns ns ns ns ns ns ns ns
NOTE
Note 4
Table 17: Host Parallel Write Cycle Timing Note: 4.
HPOEN must be asserted high while HPCSN low during a Host Parallel Write Cycle.
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IRMCK203
Discrete I/O Electrical Characteristics
START/STOP FLTCLR tL
Figure 11: Discrete I/O Timing
SYMBOL tL
DESCRIPTION Pulse Width STARTSTOP Pulse Width FLTCLR
MIN 100 1
MAX
UNITS ns us
Table 15: Discrete I/O Timing
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IRMCK203
Motion Peripheral Electrical Characteristics
PWM Electrical Characteristics
tDEADTIMERESOLUTION SYNC PWMUH PWMUL PWMVH PWMVL PWMWH PWMWL
tDEADTIMERESOLUTION
Figure 12: PWM Timing
SYMBOL tDEADTIMERESOLUTION
DESCRIPTION Deadtime Insertion Logic Resolution Table 16: PWM Timing
30
UNITS ns
IR2175 Interface
tIFB tIFBH IFB0 IFB1 tIFBL
Figure 13: IR2175 Interface
SYMBOL fIFB tIFB tIBH tIFBH
DESCRIPTION Current Feedback Input Frequency Current Feedback Period Current Feedback High Pulse Width Current Feedback Low Pulse Width Table 17: IR2175 Interface
MIN 95 10.52 500 ns 500 ns
MAX 165 6.06 10 us 10 us
UNITS kHz us
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28
Analog Interface Electrical Characteristics
ADC Timing
System Level Timing The IRMCK203 contains logic to drive an ADC Converter, Analog MUX and associated Sample and Hold circuits. Figure 14 shows the system level timing of these elements. The IRMCK203 is specifically designed to interface to the Burr-Brown ADS7818 ADC. As such, all interface signals between the ADC and IRMCK203 are guaranteed to meet worst case timing specifications over the IRMCK203 and ADS7818 specified operation environment. For interfacing to other ADCs, please contact International Rectifier for detailed specifications. Also refer to the Application Developers Guide for a detailed description of ADC, MUX and Sample and Hold signal system level protocol.
RESSAMPLE ADCONVST ADMUX0 ADMUX1 ADMUX2 ADCLK
tMUX[2:0] t1
t2
t3 tADCLK tCLKDLY
Figure 14: Top Level ADC Timing
SYMBOL tMUX[2:0] t1 t2 t3 tADCLK tCLKDLY
DESCRIPTION ADCONVST to MUX[2:0] ADCONVST Low Period ADCONVST High Period ADCONVST to ADCLK Falling ADCLK Period ADCLK STALL Period
TYP 22 1.44 630 60 127.5 210
UNITS ns us ns ns ns ns
Table 18: Top Level ADC Timing
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PLL Interface Electrical Characteristics
PARAMETER Current Consumption Current Consumption Peak jitter Cycle jitter Lock-up Time PLL Reset Period SYMBOL IDDS IDD Tpj Tcj Tlock Trst CONDITIONS Static Dynamic Recommended operating condition MIN -500 10 TYP 5 MAX 170 1000 +500 1 UNITS uA MA ps ps ms Ns
Table 20: PLL Electrical Characteristics
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IRMCK203 Appendix A
Register Access
A host computer controls the IRMCK203 using its slave-mode Full-Duplex SPI port, a standard RS-232 port or a 8-bit parallel port for connection to a microprocessor. All interfaces are always active and can be used interchangeably, although not simultaneously. Control/status registers are mapped into a 128-byte address space.
Host Register Map
Host Parallel Access
The IRMCK203 contains an address register that is updated with the Host Register address when HPA = 1. After each subsequent data byte is either read or written, the internal address register is incremented. The diagram below shows that Data Bytes 0 to N would access register locations initially specified by the Address Byte. The Address Byte with the HPA signal can be asserted at any time.
Address Byte HPA = 1
Data Byte 0 HPA = 0
................
Data Byte N HPA = 0
HPA = 0
Host Parallel Data Transfer Format
SPI Register Access
When configured as an SPI device read only and read/write operations are performed using the following transfer format:
................
Command Byte
Data Byte 0
Data Byte N
Data Transfer Format
7
Read Only
6
5
Bit Position 4 3
2
1
0
Register Map Starting Address
Command Byte Format Data transfers begin at the address specified in the command byte and proceed sequentially until the SPI transfer completes. As in the Host Parallel Access, the internal address register is incremented after each SPI byte is transferred. Note that accesses are read/write unless the "read only" bit is set.
RS-232 Register Access
The IRMCK203 includes an RS-232 interface channel that provides a direct connection to the host PC. The software interface combines a basic "register map" control method with a simple communication protocol to accommodate potential communication errors.
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IRMCK203
RS-232 Register Write Access A Register write operation consists of a command/address byte, byte count, register data and checksum. When the IRMCK203 receives the register data, it validates the checksum, writes the register data, and transmits and acknowledgement to the host.
Command / Address Byte
Byte Count
1-6 bytes of register data
Checksum
Register Write Operation
Command Acknowledgement Byte
Checksum
Register Write Acknowledgement
7
1=Read/ 0=Write
6
5
Bit Position 4 3
2
1
0
Register Map Starting Address
Command/Address Byte Format
7
1=Error/ 0=OK
6
5
Bit Position 4 3
2
1
0
Register Map Starting Address
Command Acknowledgement Byte Format The following example shows a command sequence sent from the host to the IRMCK203 requesting a two-byte register write operation: 0x2F Write operation beginning at offset 0x2F 0x02 Byte count of register data is 2 0x00 Data byte 1 0x04 Data byte 2 0x35 Checksum (sum of preceding bytes, overflow discarded) A good reply from the IRMCK203 would appear as follows: 0x2F Write completed OK at offset 0x2F 0x2F Checksum An error reply to the command would have the following format: 0xAF Write at offset 0x2F completed in error 0xAF Checksum
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IRMCK203
RS-232 Register Read Access A register read operation consists of a command/address byte, byte count and checksum. When the IRMCK203 receives the command, it validates the checksum and transmits the register data to the host.
Command / Address Byte
Byte Count
Checksum
Register Read Operation
Command Acknowledgement Byte
Register Data
(Byte Count bytes)
Checksum
Register Read Acknowledgement (transfer OK)
Command Acknowledgement Byte
Checksum
Register Read Acknowledgement (error) The following example shows a command sequence sent from the host to the IRMCK203 requesting four bytes of read register data: 0xA0 Read operation beginning at offset 0x20 (high-order bit selects read operation) 0x04 Requested data byte count is 4 0xA4 Checksum A good reply from the IRMCK203 might appear as follows: 0x20 Read completed OK at offset 0x20 0x11 Data byte 1 0x22 Data byte 2 0x33 Data byte 3 0x44 Data byte 4 0xCA Checksum An error reply to the command would have the following format: 0xA0 Read at offset 0x20 completed in error 0xA0 Checksum
RS-232 Timeout The IRMCK203 receiver includes a timer that automatically terminates transfers from the host to the IRMCK203 after a period of 32 msec. RS-232 Transfer Examples The following example shows a normal exchange executing a register write access.
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IRMCK203
The example below shows a normal register read access exchange.
The following example shows a register write request that is repeated by the host due to a negative acknowledgement from the IRMCK203.
In the final example, the host repeats a register read access request when it receives no response to its first attempt.
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IRMCK203
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IRMCK203
Write Register Definitions
PwmConfig Register Group (Write Registers)
Byte Offset 7 0xC 0xD 0xE 0xF 0x44 0x45 0x51
TwoPhs Pwm (W) TwoPhs Type (W) Gatekill Sns (W)
6
SPARE
5
Gate SnsL (W)
Bit Position 4 3
Gate SnsU (W) SyncSns
2
BrakeSns
1
SD (W)
0
SPARE
PwmPeriod (LSBs) (W) PwmConfig (W) PwmDeadTm (W) ModScl (LSBs) (W) ModScl (MSBs) (W) PwmGuardBand (W) PwmPeriod (MSBs) (W)
PwmConfig Write Register Map
Field Name SD BrakeSns SyncSns GateSnsU GateSnsL GatekillSns PwmPeriod PwmConfig TwoPhsType
Access (R/W) W W W W W W W W W
Field Description Shutdown control output to IR2137. Logic Sense for BRAKE signal output to gate driver IC. 0 = Active low, 1 = active high. Logic Sense for PWM SYNC signal output to microprocessor. 0 = Active low, 1 = active high. Upper IGBT gate sense. 1 = active high gate control, 0 = active low gate control. Lower IGBT gate sense. 1 = active high gate control, 0 = active low gate control. GATEKILL signal sense. 1 = active high GATEKILL, 0 = active low GATEKILL. PWM Carrier period. Actual PWM carrier period is 2 * (PwmPeriod + 1) * (System Clock Period). PWM Configuration. 0 = Asymmetrical center aligned PWM, 1 = Symmetrical Center aligned PWM. Used only for two-phase PWM modulation mode: 0 = Type 1 2-phase PWM 1 = Type 2 2-phase PWM Selects PWM modulation mode: 0 = Enable 3-phase space vector PWM modulation 1 = Enable 2-phase space vector PWM modulation
TwoPhsPwm
W
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IRMCK203
Field Name PwmDeadTm Access (R/W) W Field Description
ModScl
PwmGuardBand
Gate drive dead time in units of system clock cycles (e.g., 30 ns with 33 MHz clock). Space vector modulator scale factor. This register, which depends on the PWM carrier frequency, should be set as follows: W ModScl = PwmPeriod * sqrt(3) * 4096 / 2355 where PwmPeriod is the value in the PwmConfig write register group's PwmPeriod register. W This parameter provides a guard band (scaling: 1 = 30nsec) such that PWM switching will not migrate into the current feedback sampling instant (Sync Pulse region). This guard band is provided to improve feedback noise. The parameter only applies to the 3phase Space Vector modulation scheme. Please do not modify this parameter without consulting a motor drive FAE. PwmConfig Write Register Field Definitions
CurrentFeedbackConfig Register Group (Write Registers)
Byte Offset 7 0x15 0x16 0x7D 6 5 Bit Position 4 3
IfbkScl (LSB) (W) IfbkScl (MSB) (W) OffsetCalDelay (W)
2
1
0
CurrentFeedbackConfig Write Register Map
Field Name IfbkScl
Access (R/W) W
Field Description
IfbOffsVOffse tCal Delay
Rotating frame Iq component and Id component current feedback scale factor. Constant used to scale current measurements before they are used in the field orientation calculation. This is a 15-bit fixedpoint signed number with 10 fractional bits that ranges from -16 to + 16 + 1023 / 1024. This parameter specifies the delay time (1 = 1 sec) to restart current W offset measurement after a stop command is issued. Only applies if Leg Shunt current feedback is selected.12-bit signed value for V phase current feedback offset. When the IfbOffsEnb bit in the SystemControl write register group is "0" this value is automatically added to each current measurement in hardware. CurrentFeedbackConfig Write Register Field Definitions
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IRMCK203
SystemControl Register Group (Write Registers)
Byte Offset 7 0x17 6 5
SPARE
Bit Position 4 3
2
HostEstop
1
StartCmd
0
Rotation
SystemControl Write Register Map
Field Name Rotation StartCmd HostEstop
Access (R/W) W
Field Description
Direction of motor rotation: 0 = Reverse motor rotation; 1 = Forward motor rotation. W Start/Stop bit. Setting this bit to 1 issues a start command. Setting this bit to 0 stops the motor. W Emergency coast stop will take place when this bit is set to one. SystemControl Write Register Field Definitions
TorqueLoopConfig Register Group (Write Registers)
Byte Offset 7 0x1A 0x1B 0x1C 0x1D 0x22 0x23 0x26 0x27 6 5 Bit Position 4 3
2
1
0
KpIreg - Current Loop Proportional Gain (LSBs) (W) KpIreg - Current Loop Proportional Gain (MSBs) (W) KxIreg - Current Loop Integral Gain (LSBs) (W) KxIreg - Current Loop Integral Gain (MSBs) (W) VqLim - Quadrature Current Output Limit (LSBs) (W) VqLim - Quadrature Current Output Limit (MSBs) (W) VdLim - Direct Current Output Limit (LSBs) (W) VdLim - Direct Current Output Limit (MSBs) (W)
TorqueLoopConfig Write Register Map
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IRMCK203
Field Name KpIreg KxIreg VqLim VdLim Access (R/W) W W W W Field Description 15-bit signed current loop PI controller proportional gain. Scaled with 14 fractional bits for an effective range of 0 - 1. 15-bit signed current loop PI controller integral gain. Scaled with 19 fractional bits for an effective range of 0 - .03125. 16-bit Quadrature current PI controller voltage output limit. 16-bit Direct current PI controller voltage output limit. TorqueLoopConfig Write Register Field Definitions
VelocityControl Register Group (Write Registers)
Byte Offset 7 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F 0x7A 6 5 Bit Position 4 3
2
1
0
KpSreg - Velocity loop proportional gain (LSBs) (W) KpSreg - Velocity loop proportional gain (MSBs) (W) KxSreg - Velocity loop integral gain (LSBs) (W) KxSreg - Velocity loop integral gain (MSBs) (W) MotorLim - Velocity loop Output Positive Limit (LSBs) (W) MotorLim - Velocity loop Output Positive Limit (MSBs) (W) RegenLim - - Velocity loop Output Negative Limit (LSBs)
RegenLim - - Velocity loop Output Negative Limit (MSBs)
SpdScl - Speed Scale Factor (LSBs)
SpdScl - Speed Scale Factor (MSBs)
TargetSpd - Setpoint/target speed (LSBs)
TargetSpd - Setpoint/target speed (MSBs)
AccelRate
DecelRate
MinSpd
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IRMCK203
Byte Offset 7 0x18 0x19 6 5 Bit Position 4 3
StartLim (LSBs)
2
1
0
StartLim (MSBs)
VelocityControl Write Register Map
Field Name KpSreg KxSreg MotorLim RegenLim
Access (R/W) W W W W
Field Description
SpdScl
W
TargetSpd AccelRate DecelRate MinSpd StartLim
W W W W W
15-bit velocity loop proportional gain, in fixed point with 5 fractional bits. Range = 0 - 512. 15-bit velocity loop integral gain, in fixed point with 13 fractional bits. Range = 0 - 2. Motoring torque current limit (4095 = rated motor current).16-bit speed PI controller output positive limit. Regeneration torque current limit (4095 = rated motor current)16-bit speed PI controller output negative limit (2's complement).. Motor Speed Scale factor. Spd value (in the VelocityStatus read register group) is maintained in SPEED units of SpdScl * (Encoder counts / Velocity Loop Execution) or SpdScl * (RATE * Encoder counts / PWM period). The user should set SpdScl = (64 * 16384) * 60 * PWMFREQ / (RATE * Max RPM * Encoder counts/revolution), which will result in a Spd value ranging 16384 corresponding to Max RPM. Velocity loop speed setpoint in SPEED units, which are determined by the user via the SpdScl register setting. Positive speedAcceleration rate limit. Negative speedDeceleration rate limit. Minimum speed protection. This parameter sets the minimum reference speed. Drive start-up current limit. (4095 = rated motor current). VelocityControl Write Register Field Definitions
FaultControl Register Group (Write Registers)
Byte Offset 7 0x42 6 5
SPARE
Bit Position 4 3
2
1
FltClr
0
DcBusM Enb
FaultControl Write Register Map
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IRMCK203
Field Name
Access (R/W)
Field Description DC Bus monitor enable. 1 = Monitor DC bus voltage and generate appropriate brake signal control and disable PWM output when voltage fault conditions occur. GatekillFlt and OvrSpdFlt faults cannot be disabled. DC bus voltage thresholds are as follows: Overvoltage - 410V Brake On - 380V Brake Off - 360V Nominal - 310V Undervoltage off - 140V Undervoltage - 120V This bit clears all active fault conditions. The user should monitor the FaultStatus read register group to determine fault status and set this bit to "1" to clear any faults that have occurred. A fault condition automatically clears the PwmEnbW and FocEnbW bits in the SystemControl write register group. Note that this bit also directly controls the output 2137 FLTCLR pin. After clearing a fault, the user must explicitly set this bit to "0" to re-enable fault processing. FaultControl Write Register Field Definitions
DcBusMEnb
W
FltClr
W
SystemConfig Register Group (Write Registers)
Byte Offset 7 0x50
ExtCtrl
6
AdcIfbEnb
5
Ramp Stop
Bit Position 4 3
2
SPARE
1
0
SystemConfig Write Register Map
Field Name RampStop
Access (R/W) W
Field Description
AdcIfbEnb
ExtCtrl
Selects the stopping mode: 0 - Configure for Coast stopping 1 - Configure for Ramp stopping W Selects the current feedback mode: 0 - Selects IR2175 current feedback 1 - Selects Leg-Shunt current feedback Setting this bit to "1" enables direct control of basic motor operation W via the external User Interface pins. When this bit is "1", the FocEnbW and PwmEnbW bits in the SystemControl write register group are ignored. SystemConfig Write Register Field Definitions
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IRMCK203
EepromControl Registers (Write Registers)
At power up, the write registers can be optionally initialized with values stored in EEPROM. The EepromControl write register group and EepromStatus read register group are used to read and write these EEPROM values. Since the EeAddrW write register (which selects the EEPROM offset to read or write) does not require initialization at power up, the location corresponding to that register in EEPROM (at offset 0x5D) is used to store a register map version code. At power on, the IRMCK203 initializes the write registers from EEPROM only if the version code stored at this offset in EEPROM matches its internal register map version code (which can be read from the RegMapVer field of the EepromStatus read register group). To enable write register initialization at power up, write the appropriate register map version code to EEPROM at offset 0x5D. To disable write register initialization at power up, write a zero (or any non-matching version code) to offset 0x5D of the EEPROM. Byte Offset 7 0x5C 0x5D 0x5E 6 5
SPARE
Bit Position 4 3
2
EeWrite
1
EeRead
0
EeRst
EeAddrW / RegMapVersCode (W) EeDataW (W)
EepromControl Write Register Map
Field Name EeRst EeRead
Access (R/W) W W
Field Description
EeWrite
W
EeAddrW EeDataW
W W
Self-clearing EEPROM reset. Writing a "1" to this bit resets the I2C EEPROM interface. Self-clearing I2c EEPROM Read. Writing a "1" to this bit initiates an EEPROM read from the byte located at EEPROM address EeAddrW. After setting this bit the user should poll the EeBusy bit in the EepromStatus read register group to determine when the read completes and then read the data from EeDataR in the EepromStatus read register group. Self-clearing EEPROM Write. Writing a "1" to this bit initiates an EEPROM write from the data byte in EeDataW to the EEPROM address EeAddrW . EEPROM Address Register. Contains the address for the next EEPROM read or write operation. EEPROM Data Register. Contains the data for the next EEPROM write operation. EepromControl Write Register Field Definitions
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IRMCK203
ClosedLoopAngleEstimator Registers (Write Registers)
Byte Offset 7 0x60 0x61 0x62 0x63 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77
SPARE SPARE SPARE
6
5
Bit Position 4 3
IScl (LSBs) (W) IScl (MSBs (W) FlxBInit (LSBs) (W) FlxBInit (MSBs) (W) PllKp (LSBs) (W)
2
1
0
PllKp (MSBs (W) PllKi (LSBs) (W) PllKi (MSBs (W) VoltScl (LSBs) (W) VoltScl (MSBs (W) Rs (LSBs) (W) Rs (MSBs (W) Ld (LSBs) (W) Ld (MSBs (W) AtanTau (LSBs) (W) AtanTau (MSBs (W) FlxTau (LSBs) (W) FlxTau (MSBs) (W)
ClosedLoopAngleEstimator Write Register Map
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IRMCK203
Field Name IScl FlxBInit PllKp PllKi VoltScl Rs Ld AtanTau FlxTau Access Field Description (R/W) W Current scaler for motor flux calculation. W Initialization value of Beta flux at start. W Flux phase lock loop proportional gain. W Flux phase lock loop integral gain. W Voltage scaler for motor flux calculation. W Motor per phase resistance including cable (@25C). W Motor per phase inductance. W Rotor angle estimator phase compensation gain. W Rotor angle estimator flux model time constant. ClosedLoopAngleEstimator Write Register Field Definitions
OpenLoopAngleEstimator Registers (Write Registers)
Byte Offset 7 0x66 0x67 0x5F 6 5 Bit Position 4 3
KTorque (LSBs) (W) KTorque (MSBs (W) VFGain (W)
2
1
0
OpenLoopAngleEstimator Write Register Map
Field Name KTorque VFGain
Access Field Description (R/W) W Motor mechanical model torque constant. W Open-Loop Volts/Hz Flux gain. (for diagnostic use only). OpenLoopAngleEstimator Write Register Field Definitions
StartupAngleEstimator Registers (Write Registers)
Byte Offset 7 0x64 0x65 0x68
SPARE Zero SpdFlt Disable Use2xFrq Scale
6
5
Bit Position 4 3
ParkI (W) PhsLosFlt Disable WeThr (LSBs) (W)
2
1
0
DiagnosticCtrl (W)
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IRMCK203
Byte Offset 7 0x69 0x78 6 5 Bit Position 4 3
WeThr (MSBs (W) ParkTm (W)
2
1
0
StartupAngleEstimator Write Register Map
Field Name ParkI DiagnosticCtrl
Access (R/W) W W
Field Description
PhsLosFlt Disable Use2xFrqScale
ZeroSpdFlt Disable WeThr ParkTm
DC current injection level during motor parking (start-up mode). 1 (0001) - Enable Parking diagnostic 2 (0010) - Enable start-up diagnostic 5 (0101) - Enable current regulator diagnostic 9 (1001) - Enable volts Hertz diagnostic W Enable/disable phase loss fault: 0 = Enable Phase Loss Fault; 1 = Disable Phase Loss Fault W Selects speed scaling: 0 - Norminal speed scale 1 - Reduce speed feedback scaling by half Please do not modify this parameter without consulting motor control FAEs W Zero speed fault enable/disable: 0 - Enbale Zero Speed Fault 1 - Disable Zero Speed Fault W Frequency threshold level (switch over from open-loop to closedloop mode). W Time duration of parking mode. 255 = 4 sec StartupAngleEstimator Write Register Field Definitions
StartupRetrial Registers (Write Registers)
Byte Offset 7 0x1E 0x1F 0x79 0x7B 0x7C 6 5 Bit Position 4 3
RetryTm (LSBs)
2
1
0
RetryTm (MSBs)
ParkTmRet
FlxThrL
FlxThrH
This document is the property of International Rectifier and may not be copied or distributed without expressed consent.
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IRMCK203
Byte Offset 7 0x7E 0x7F 6 5 Bit Position 4 3
NumRetries
2
1
0
ParkIRet
StartupRetrial Write Register Map
Field Name RetryTm
Access (R/W) W
Field Description
ParkTmRet
W
FlxThrL
W
FlxThrH
W
NumRetries
W
ParkIRet
W
This parameter provides the adjustment to the sampling instant for determination of start failure. The sampling instant starts when Closed_Loop = 1. Scaling 1 count = 1.966 msec. Please do not modify this parameter without consulting a motor drive FAE. During motor start-up, dc current is injected to the motor for maximization of startup torque per ampere rating. ParkTm controls the duration of dc current injection. However, users are able to use a longer duration after two or more restarts by setting this parameter (ParkTmRet scaling 255 = 4 secs.). This is done to increase the chance of a successful start-up.Start-up failure may be caused by increased shaft friction. After first start-up retry, the parking time can be increased to improve parking performance. The low flux threshold level for determining a successful startup (scaling: 129 = 100% flux). Please do not modify this parameter without consulting a motor drive FAE.The low flux threshold level for determining a successful startup. The upper flux threshold level for determining a successful startup (scaling: 64 = 100% flux). Please do not modify this parameter without consulting a motor drive FAE.The high flux threshold level for determining start-up failure. If start-up fails, the user can program start-up retrial. This parameter determines the number of start-up retries. A value of zero will disable startup retrial. The maximum number of retries is 15. During motor start-up, dc current is injected to the motor for maximization of startup torque per ampere rating. Users are able to use a higher level of dc current injection (ParkIRet scaling 255 = Motor Rated Amp * 0.866) after two or more restarts. This is done to increase the chance of a successful start-up.Start-up failure may be caused by increased shaft friction. After first start-up retry, the parking current can be increased to improve parking performance. StartupRetrial Write Register Field Definitions
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IRMCK203
PhaseLossDetect Registers (Write Registers)
Byte Offset 7 0x79 0x28 0x29 0x2A 6 5 Bit Position 4 3
ParkTmRet
2
1
0
AdjPark1
AdjPark2
RetryTm
PhaseLossDetect Write Register Map
Field Name AdjPark1 AdjPark2 PhsLosThr
Access (R/W) W
Field Description
Anticipated W-phase motor current gain scaler used during initial stage of Phase Loss detection. W Anticipated W-phase motor current gain scaler used during final stage of Phase Loss detection. W Phase Loss detection current error thershold. PhaseLossDetect Write Register Field Definitions
D/AConverter Registers (Write Registers)
Byte Offset 7 0x4F 6 5 Bit Position 4 3
DacSel
2
1
0
D/AConverter Write Register Map
This document is the property of International Rectifier and may not be copied or distributed without expressed consent.
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IRMCK203
Field Name DacSel
Access (R/W) W
Field Description
Selects D/A converter diagnostic outputs 0 - 3. A value of 0 selects: Data 0 = Alpha fluxFlux Data 1 = Electrical Rotor angle Data 2 = Alpha voltageTorque current Data 3 = Closed loop/open loop status (0 = open, 1 = closed) A value of 1 selects: Data 0 = Alpha currentDC bus voltage Data 1 = Torque current feedbackAlpha voltage Data 2 = IQ refTorque current reference Data 3 = Motor speed A value of 2 selects: Data 0 = Q-axis command voltage Data 1 = D-axis command voltage Data 2 = Alpha current Data 3 = Beta current A value of 3 selects: Data 0 = Flux magnitude Data 1 = Current error at parking Data 2 = Parking diagnostic flag Data 3 = W-phase current D/AConverter Write Register Field Definitions
Factory Test Register (Write Register)
Byte Offset 7 0x58 6 5 Bit Position 4 3
Test
2
1
0
Factory Write Register Map
Field Name Test
Access (R/W) W
Field Description Reserved for factory use. Data written to this register could be read from a read register at location 0x58. Factory Write Register Field Definitions
This document is the property of International Rectifier and may not be copied or distributed without expressed consent.
48
IRMCK203
Read Register Definitions
SystemStatus Register Group (Read Registers)
Byte Offset 7 0x7
StartStop
6
FwdRev
5
ESTOP
Bit Position 4 3
PwrID
2
ExtCtrlR
1
Foc EnbR
0
Pwm EnbR
SystemStatus Read Register Map
Field Name PwmEnbR FocEnbR ExtCtrlR PwrID ESTOP FwdRev
Access (R/W) R R R R R R
Field Description
StartStop
R
PWM Enable bit status. FOC Enable bit status. Reflects the status of the ExtCtrl bit in the System Configuration write register (address 0x50). Power ID. 0 = 3 kW, 1 = 2 kW, 2 = 500 W. User Interface emergency stop signal (1 - emergency stop) User Interface "FWD/REVDIR" digital input status. 1 - Forward rotation request 0 - Reverse rotation request User Interface "START/STOP" digital input status. 1 - Start 0 - Stop SystemStatus Read Register Field Definitions
DcBusVoltage Register Group (Read Registers)
Byte Offset 7 0xA 0xB
SPARE
6
5
Bit Position 4 3
DcBusVolts (LSBs)
2
1
0
Brake
DcBusVolts (MSBs)
DcBusVoltage Read Register Map
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49
IRMCK203
Field Name DcBusVolts Brake
Access (R/W) R R
Field Description
DC Bus Voltage. Data range is 0 - 4095, which corresponds to a DC bus voltage between 0 and 500 volts. Brake signal status. 1 = Brake signal active. DcBusVoltage Read Register Field Definitions
FocDiagnosticData Register Group (Read Registers)
Byte Offset 7 0xC 0xD 0xE 0xF 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19
SPARE Parking Done Start_ Fail
6
5
Bit Position 4 3
RotatorAngle (LSB)
2
1
0
Closed_ Loop
RotatorAngle (MSB)
Id - Synchronous Frame Direct Current (LSBs)
Id - Synchronous Frame Direct Current (MSBs)
Iq - Synchronous Frame Quadrature Current (LSBs)
Iq - Synchronous Frame Quadrature Current (MSBs)
IqRef_C - Synchronous Frame Quadrature Current command (LSB)
IqRef_C - Synchronous Frame Quadrature Current command (MSB)
Flx_Alpha - Estimated Motor Flux (LSB)
Flx_Alpha - Estimated Motor Flux (MSB)
I_Alpha - Alpha Frame Current (LSB)
I_Alpha - Alpha Frame Current (MSB)
V_Alpha - Alpha Frame Voltage (LSB)
V_Alpha - Alpha Frame Voltage (MSB)
FocDiagnosticData Read Register Map
This document is the property of International Rectifier and may not be copied or distributed without expressed consent.
50
IRMCK203
Field Name RotatorAnlge Access (R/W) R Field Description
Closed_Loop
Start_Fail
Parking Done Id, Iq
IqRef_C Flx_Alpha I_Alpha
V_Alpha
Estimated rotor angle (electrical), which is used for synchronous frame to stationary frame transformation. The scaling is 4096 = 2PI. The range is 0 - 4095. This is a drive control status flag which indicates that the drive has R switched from open-loop to closed-loop operation. The switch over is done during drive start-up (initial speed ramping) This is a drive control status flag indicating that the drive has failed to R start due to various reasons (for instance: shaft jam). The start-stop sequencer uses this bit and parameter NumRetry to determine whether a start-up retry should be activated. This is a status flag indicating that the drive has finished obtaining the R initial rotor angle (parking) for motor startup. During drive start-up, the first start-up stage is parking stage. Synchronous or rotating frame direct and quadrature current values R in 2's complement representation. The full scale current values range from -16384 to 16383. (Scaling: 4095 = rated motor current) Synchronous or rotating frame quadrature current command values R in 2's complement representation. The full scale current values range from -16384 to 16383. R Estimated motor flux value. Scaling is 5000 = rated motor flux. Stationary frame current. Scaling is platform dependent (current R shunt resistor). Drive commissioning tool (Spreadsheet) provides the scaling of I_Alpha (AiBi scale). Stationary frame Alpha voltage. This voltage is constructed by dc bus R voltage and modulation index in the Stationary frame. The scaling is platform dependent. FocDiagnosticData Read Register Field Definitions
FaultStatus Register Group (Read Registers)
The Fault Status register records fault conditions that occur during drive operation. When any of these fault conditions occur, the PWM output is automatically disabled. The user should monitor this register continuously for fault conditions. A fault condition can be cleared by writing a "1" to the FaultClr bit in the FaultControl write register group. (This does not automatically re-enable PWM output.) Byte Offset 7 0x1E
PhsLoss Flt
6
RetryFlt
5
ZeroSpd Flt
Bit Position 4 3
ExecTm Flt OvrSpdFlt
2
OvFlt
1
LvFlt
0
GatekillFlt
FaultStatus Read Register Map
Field Name GatekillFlt LvFlt
Access (R/W) R R
Field Description Filtered and latched version of IR2137 FAULT output. DC bus low voltage fault. This fault occurs if the DC bus drops below 120V.
This document is the property of International Rectifier and may not be copied or distributed without expressed consent.
51
IRMCK203
Field Name OvFlt Access (R/W) R Field Description DC bus overvoltage fault. This fault occurs if the DC bus voltage exceeds 410V. Over speed fault. This fault occurs whenever the motor reaches the positive or negative limits. The user should use the scale factor in the SpdScl field of the VelocityControl write register group to scale the motor speed so that it falls between -16384 and +16383 with these limits as the over speed condition. Execution time fault. Zero Speed fault. When speed is less than MinSpd/2 (half minimum speed) for a continuous period of 2 4 seconds, the zero speed fault will be set. Start-up retry fault. After a certain number (determined by parameter NumRetries) of start-up failures, this fault will be set. Phase loss fault. Drive to motor phase connection may be loose. FaultStatus Read Register Field Definitions
OvrSpdFlt
R
ExecTmFlt ZeroSpdFlt
R R
RetryFlt PhsLossFlt
R R
VelocityStatus Register Group (Read Registers)
Byte Offset 7 0x26 0x27 6 5 Bit Position 4 3
Spd (LSBs)
2
1
0
Spd (MSBs)
VelocityStatus Read Register Map
Field Name Spd
Access (R/W) R
Field Description
Current motor speed in SPEED units. (See the description of SpdScl in the VelocityControl write register group.) VelocityStatus Read Register Field Definitions
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IRMCK203
CurrentFeedbackOffset Register Group (Read Registers)
Byte Offset 7 0x30 0x31 0x32
IfbWOffs (LSBs) (R) IfbWOffs (MSBs) (R)
6
5
Bit Position 4 3
IfbVOffs (LSBs) (R)
2
1
0
IfbVOffs (MSBs) (R)
CurrentFeedbackOffset Read Register Map
Field Name IfbVOffs, IfbWOffs
Access (R/W) R
Field Description
Current feedback offset values from the last IFB Offset calculation. These values are automatically applied to each current feedback measurement value whenever the IfbOffsEnb bit in the SystemControl write register group is set. CurrentFeedbackOffset Read Register Field Definitions
EepromStatus Registers (Read Registers)
Byte Offset 7 0x38 0x39 0x3A 6 5 Bit Position 4 3
SPARE
2
1
0
EeBusy
EdDataR (R) EeAddrR (R)
EepromStatus Read Register Map
Field Name EeBusy
Access (R/W) R
Field Description I2C EEPROM Interface busy bit. The user should wait for this bit to clear before initiating EEPROM read or write operations.
This document is the property of International Rectifier and may not be copied or distributed without expressed consent.
53
IRMCK203
Field Name EeDataR Access (R/W) R Field Description
EeAddrR
R
EEPROM Data Register. Contains the data from the last EEPROM read operation. Note that writing to the EeRst field in the EepromControl write register group invalidates this register. EEPROM Address read register shows the value stored in EEPROM at the offset of the EeAddrW write register (0x5D). Since this address in the EEPROM contains the BPIRMCK203 register map version, the user can read this field to determine whether or not the write registers were initialized at power on. EepromStatus Read Register Field Definitions
FOCDiagnosticDataSupplement Register Group (Read Registers)
Byte Offset 7 0x3C 0x3D 0x3E 0x3F 0x40 0x41 0x42 0x43
SPARE
6
5
Bit Position 4 3
ElecAngR (LSBs) (R)
2
1
0
ElecAngR (MSBs) (R) SpdRef (LSBs) (R) SpdRef (MSBs) (R) SpdErr (LSBs) (R) SpdErr (MSBs) (R) IqRefR (LSBs) (R) IqRefR (MSBs) (R)
FOCDiagnosticDataSupplement Read Register Map
Field Name ElecAngR SpdRef SpdErr IqRefR
Access Field Description (R/W) R Electrical angle. R Speed PI controller reference input. R Speed PI controller error. R Speed PI controller output. FOCDiagnosticDataSupplement Read Register Field Definitions
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IRMCK203
ProductIdentification Registers (Read Registers)
Byte Offset 7 0x7C 0x7D 0x7E 0x7F 6 5 Bit Position 4 3
ProductID (R) RegMapVerID (R) RevCodeID (LSBs) (R) RevCodeID (MSBs) (R)
2
1
0
ProductIdentification Read Register Map
Field Name ProductID RegMapVerID RevCodeID
Access (R/W) R R R
Field Description
Product identification code. Current register map version code. IRMCK203 Revision Code. Revision code format is "XX.XX", where each "X" is a 4-bit hexadecimal number. ProductIdentification Read Register Field Definitions
Factory Register (Read Register)
Byte Offset 7 0x58 6 5 Bit Position 4 3
Test (R)
2
1
0
Factory Read Register Map
Field Name Test
Access (R/W) R
Field Description Data value resulting from a write to write register 0x58. factory use only. Factory Read Register Field Definitions Used for
This document is the property of International Rectifier and may not be copied or distributed without expressed consent.
55
IRMCK203
Appendix B
Package
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56
IRMCK203
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 252-7105 Data and specifications subject to change without notice. 4/13/2004 http://www.irf.com
Sales Offices, Agents and Distributors in Major Cities Throughout the World.
This document is the property of International Rectifier and may not be copied or distributed without expressed consent.
57

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